|Let’s now talk for a minute about the actual hardware side of the Sitcom. Nothing complicated to be sure, but a reliable, useable and expandable circuit that should fulfil the needs of the microprocessor experimenter. To the right we see the second almost complete and working prototype, at this stage under the control of half a dozen lines of code in an EEPROM, rather than the Sitcom Boot PROM. Sometimes it is a good idea to test this way if you feel like exercising a particular feature independently. Note that the project doesn’t have any divider chips, RS232 or experimenters I/O ports connected just yet.|
|SITCOM BLOCK DIAGRAM|
|So onto the main Sitcom block diagram as seen below. Note that hardly any of the control lines are shown for simplicity and clarity. The 8085 has what is called a MULTIPLEXED data and address bus. This means that the same pins are used for the data bus as well as for the eight, lower order address lines. They are split up using the 373 latch chip controlled by the ALE line (Address Latch Enable). The 8255 is a programmable I/O port (PPI) with 24 parallel lines. Plenty of options for those all-important experiments! The 138 decoder chip is strictly for the I/O devices in the circuit, controlling the PPI, the two optional displays, plus up to another 5 future devices with no further decoding. The RS232 interface is a simple transistor level converter, driving the 8085’s built-in Serial Input Data pin (SID).|
|GLUE LOGIC AND MEMORY SELECTION|
|The ‘glue’ logic and memory switching in the diagram below is not complex, but performs the task of coordinating the resetting, running and memory allocation to the 8085. Using the two buttons, we are therefore able to start or stop a download and direct the processor to either run from the Boot ROM or the downloaded program in the RAM using the signals from the two push switches, Address line A15 and the IO/M (I/O or memory select) line. We use the 8085’s SOD (Serial Output Data) line to show the status of the glue logic and the program downloading on a simple LED by using different flashing rates.|
Let us now have a quick glance at the truth table for the glue logic and memory switching.
In the diagram above we can see the cross-coupled nand gates acting as a R/S flip-flop to ‘latch’ the last known state from the buttons.
With the BOOT button down for instance, the ‘Boot’ line becomes active high and assuming that address line A15 is not HIGH, and IO/M is low (in favour of the memory) the ROM will be enabled.
If however, A15 goes high when Boot is high, then the RAM will be enabled instead as soon as IO/M goes low.
When BOOT is low, the RAM will always be selected, regardless of the logic level of A15.
This means that the RAM is accessible from address 0000H to 7FFFH, and is mirrored at the addresses 8000H to FFFFH.
In this case the Boot ROM has become totally inaccessible!
Due to a larger capacitor across the Boot switch SITCOM will always start from the Boot ROM when power is applied.
|PSU HIGH VOLTAGE & 100 / 120Hz REFERENCE|
If you were proposing to use a ready-built PSU, whilst you can use an optional frequency divider circuit to generate your 100Hz or 120Hz reference (which may be somewhat less accurate for long-term clock use) the method of generating a high voltage to program EPROMs may require a bit more thought.
* Remember that the programming High voltage output is ONLY needed if you are contemplating building an EPROM programmer facility with your Sitcom. *
|OPTIONAL 100 / 120 Hz REFERENCE|
If you propose to power your Sitcom from a supply where you will have no direct access to the low voltage AC from the transformer, (like with a plug-in type supply), you might like to consider using a pair of 4040 counters to divide down the 8085 system clock to use for experiments with delays and timekeeping. Remember though, that the long term stability of this crystal-controlled reference might well be inferior to that derived directly from the mains frequency.
If you are going to use this divider chain I recommend you use a nice "round" crystal frequency of 6.000MHz. This will allow more accurate time-keeping software at the expense of a less accurate, but still workable, baud rate with serial communication experiments.
The two prototypes have been tried out with THREE values that you can be sure WILL work.
The ideal choice is 6.144Mhz, which will produce the most accurate baud rate during communication experiments.
However, 6.000 MHz has been tried and seemed to work OK too. This value is ideal when you're using the 4040 divider chain to obtain the 100Hz or 120Hz reference signals.
The third value tried was 3.075MHz, because some of the oldest 8085’s may well not work with 6megs. Being exactly half of 6.144MHz, the baud rate is halved exactly, so this will have to be reflected in the choice of 4,800 baud within the SB-Assembler setup or the Terminal program. The speed at which any programs or experiments run at will also be halved if used with software delays. It should not however, affect any using the 100Hz signal as a timing reference.
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